IBM Bisync Block Checking Procedures
Bisync may use one of two error-checking schemes: (1) CRC-16, or (2) VRC/LRC per the following table:
The error check method used depends upon the line code, ASCII (American Standard Code for Information Interchange), or EBCDIC (IBM’s Extended Binary-Coded Decimal Interchange Code). Transparency defines a mode where bytes can be transmitted regardless of the type of code set used (proprietary modes).
In this method, both a Vertical Redundancy Check (character parity) and a Longitudinal Redundancy Check (block parity or horizontal parity) are performed. The VRC bit provides odd-parity for each character. The LRC provides odd-parity of each bit position of all characters in the block.
Errors in transmission can be detected using feedback, or convolutional coding. Using mathematical algorithms, a special code is appended to the message. The receiver calculates the algorithm based upon the received data and compares it to the appended code.
This appended code is known as a Cyclic Redundancy Check (CRC) and for IBM Bisync, is two-characters long, or 16 bits (CRC-16). The generator polynomial used is: X16 + X15 + X2 + 1
As implemented in shift registers, the CRC process has the advantage that the current shift register state is based upon the past history of bits. Therefore, it is very robust in detecting bursts of errors. CRC-16 detects all error bursts of 16 bits or less. It will also detect all errors that change an odd number of bits.